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Part I · Chapter 10

Training at Scale: Stability and Distributed Parallelism

AuthorChangkun Ou
Reading time~24 min

A training run becomes distributed for one of two reasons: the model state no longer fits on one accelerator, or one accelerator would take too long to finish the work. Distribution solves those problems by creating another one. Every shard must exchange data with its peers, and every participating worker becomes another place where the job can stop.

The design task is therefore an accounting problem. For each proposed layout, ask four questions:

  1. What is replicated, and what is sharded?
  2. What is the peak memory on each device, including temporary buffers?
  3. Which messages lie on the critical path of a step?
  4. What state must survive a restart for the run to continue correctly?

This chapter develops that accounting from a single-device training step to a multi-dimensional device mesh. The goal is not a universal recipe. Model shape, sequence length, numerical format, and network topology jointly determine the best layout.

Start with one logical optimizer step

Data parallelism is the simplest place to begin. Each of DD replicas receives a different part of the batch, runs the same model, and contributes to one synchronous gradient update. If every replica processes mm micro-batches of BμB_\mu sequences before the optimizer runs, then

Bglobal=DmBμ.B_{\mathrm{global}} = DmB_\mu.

Here, BglobalB_{\mathrm{global}} is the number of sequences in one optimizer step, DD is the data-parallel degree, mm is the number of micro-batches accumulated per replica, and BμB_\mu is the number of sequences in one micro-batch. Token counts can differ between sequences, so production runs often track tokens per step as well as sequences per step.

With equal local batch sizes, an all-reduce produces the mean gradient

g=1Dr=1Dgr,gr=1Bglobal/DiBrθi(θ).g = \frac{1}{D}\sum_{r=1}^{D}g_r, \qquad g_r = \frac{1}{B_{\mathrm{global}}/D} \sum_{i\in\mathcal B_r}\nabla_\theta \ell_i(\theta).

Here, rr indexes replicas, Br\mathcal B_r is replica rr's local batch, θ\theta is the parameter vector, i\ell_i is the loss for example ii, and grg_r and gg are the local and global mean gradients. If local batch sizes differ, averaging the replica means equally is wrong; the reduction must weight each sum by its example or token count.

This equation is the semantic contract. Different sharding schemes may change where tensors live and the order of floating-point reductions, but they should implement the same intended synchronous update. Bitwise identity is a stronger and usually topology-dependent requirement.

Account for model-state memory

Plain distributed data parallelism (DDP) replicates parameters, gradients, and optimizer state on every replica. It distributes compute and the batch, but it does not shard this persistent model state. Zero Redundancy Optimizer (ZeRO) removes the replication in stages (Rajbhandari et al. 2020):

Layout Sharded across the data-parallel group Persistent bytes per device
DDP nothing Pθ(bw+bg+bo)P_\theta(b_w+b_g+b_o)
ZeRO stage 1 optimizer state Pθ(bw+bg+bo/D)P_\theta(b_w+b_g+b_o/D)
ZeRO stage 2 optimizer state and gradients Pθ[bw+(bg+bo)/D]P_\theta[b_w+(b_g+b_o)/D]
ZeRO stage 3 parameters, gradients, and optimizer state Pθ(bw+bg+bo)/DP_\theta(b_w+b_g+b_o)/D

Here, PθP_\theta is the parameter count; bwb_w, bgb_g, and bob_o are the bytes per parameter used by working parameters, gradients, and all optimizer-related state; and DD is the data-parallel degree. For one common Adam recipe, bw=2b_w=2, bg=2b_g=2, and bo=12b_o=12: a two-byte working parameter and gradient, plus a four-byte master parameter and two four-byte moments. That recipe uses 16Pθ16P_\theta bytes before activations and temporary storage, but these dtypes are choices rather than constants of Adam.

The table is a persistent-state estimate, not a peak-memory estimate. Under full sharding, a wrapped module's parameters are gathered before computation and gradients are reduced and scattered afterward. A useful lower bound is

MpeakPθ(bw+bg+bo)D+Pubw+Mact+Mtmp.M_{\mathrm{peak}} \gtrsim \frac{P_\theta(b_w+b_g+b_o)}{D} + P_u b_w + M_{\mathrm{act}} + M_{\mathrm{tmp}}.

Here, PuP_u is the number of parameters simultaneously materialized by the current and prefetched units, MactM_{\mathrm{act}} is saved activation memory, and MtmpM_{\mathrm{tmp}} covers communication workspaces, allocator overhead, padding, and other temporary buffers. PyTorch fully sharded data parallel (FSDP) applies this full sharding idea to wrapped modules and can prefetch a later unit's parameters while the current one computes (Zhao et al. 2023). ZeRO-Infinity extends the memory hierarchy to CPU memory and NVMe storage (Rajbhandari et al. 2021).

More sharding does not make communication disappear. In the element-volume model used by the ZeRO paper, DDP and stages 1 and 2 move roughly two model copies per step, while stage 3 moves roughly three because parameters are gathered for both forward and backward computation (Rajbhandari et al. 2020). Per-device state falls as 1/D1/D; parameter-gather payload per device approaches one model copy as DD grows, while latency and topology can still make a larger group slower.

Four more ways to divide the work

Data parallelism is only one axis. A model that still does not fit, or whose layers do not run efficiently on one device, needs other cuts.

Tensor parallelism: split a layer

Tensor parallelism (TP) divides matrix multiplications within a layer. For a feed-forward block with input XX, the paired column and row partition is

Hr=ϕ(XW1(r)),Z=r=1THrW2(r).H_r=\phi(XW_1^{(r)}), \qquad Z=\sum_{r=1}^{T}H_rW_2^{(r)}.

Here, TT is the tensor-parallel degree; rr indexes its ranks; W1(r)W_1^{(r)} is a column shard of the first projection; W2(r)W_2^{(r)} is the matching row shard of the second projection; ϕ\phi is the activation function; and the sum that forms ZZ requires a reduction. Attention can similarly shard query, key, and value heads, then row-shard the output projection.

Megatron-LM's original layout arranges the attention and feed-forward blocks so that each Transformer layer has two all-reduces in its forward pass and the corresponding reductions in backward (Shoeybi et al. 2019). TP lowers per-rank parameters and arithmetic, but places communication on the critical path of every layer. It is therefore usually mapped to the fastest fabric domain available. That is a placement rule, not a law: whether a TP group may cross nodes depends on message size, topology, and the performance target.

Pipeline parallelism: split the layer stack

Pipeline parallelism (PP) assigns consecutive groups of layers to stages and streams micro-batches through them. Stage boundaries carry activations forward and their gradients backward. The stages need not coincide with nodes.

At the start and end of a synchronous flush schedule, some stages are idle. For balanced stages with negligible communication, GPipe's idealized idle fraction is (Huang et al. 2019)

fbubble=p1m+p1.f_{\mathrm{bubble}}=\frac{p-1}{m+p-1}.

Here, pp is the number of pipeline stages, mm is the number of micro-batches per replica per optimizer step, and fbubblef_{\mathrm{bubble}} is the fraction of aggregate stage slots left idle by fill and drain. This denominator matters: the often-quoted (p1)/m(p-1)/m is bubble time relative to ideal compute time, not the fraction of total stage capacity.

bubble t slot 1 2 3 4 5 6 7 stage 1 mb1 mb2 mb3 mb4 idle idle idle stage 2 idle mb1 mb2 mb3 mb4 idle idle stage 3 idle idle mb1 mb2 mb3 mb4 idle stage 4 idle idle idle mb1 mb2 mb3 mb4
Figure 10.1. One forward wave through four balanced pipeline stages. Colored cells are micro-batch work; blank cells are the fill and drain slots counted by the ideal GPipe bubble model. A full training schedule also sends activation gradients backward.

The formula is useful for sizing, not prediction. Unequal stage times, communication, optimizer work, and alternative schedules change the result. A 1F1B schedule can reduce saved activation memory without changing this ideal bubble; interleaved schedules can reduce the bubble but send more point-to-point messages (Narayanan et al. 2021). PipeDream explores asynchronous schedules and weight versions, a different optimizer-semantics tradeoff from GPipe's synchronous flush (Narayanan et al. 2019).

2026-08-03T21:54:39.255369 image/svg+xml Matplotlib v3.11.0, https://matplotlib.org/ 20 40 60 80 100 120 micro-batches per step (m) 0.0 0.2 0.4 0.6 0.8 1.0 pipeline bubble fraction 4 stages 8 stages 16 stages
Figure 10.2. Ideal GPipe bubble fraction for balanced synchronous flush schedules. The model assumes equal stage times and negligible communication; it is not measured throughput.

The calculation below makes the scale of the bubble concrete. For 32 stages and 32 micro-batches, nearly half of aggregate stage capacity is still idle in this idealized schedule.

def bubble_fraction(stages, microbatches):
    """Balanced GPipe flush schedule; communication is ignored."""
    if stages < 1 or microbatches < 1:
        raise ValueError("stages and microbatches must be positive")
    return (stages - 1) / (microbatches + stages - 1)


for stages in (4, 8, 16, 32):
    values = {
        microbatches: round(bubble_fraction(stages, microbatches), 3)
        for microbatches in (1, 4, 8, 16, 32, 64)
    }
    print(f"p={stages}: {values}")

print("p=32, m=32:", f"{bubble_fraction(32, 32):.1%}")
Figure 10.3. The ideal GPipe bubble for a balanced synchronous flush schedule with negligible communication. Increase the stage count or micro-batch count to inspect the formula; a real trace can be worse because stages are unequal and messages take time.

Sequence parallelism and context parallelism: split tokens

These names describe related but distinct mechanisms. Megatron-style sequence parallelism (SP) shards the layer-normalization, dropout, and other regions that TP otherwise replicates along the sequence dimension. It reuses the TP group and replaces selected all-reduces with reduce-scatter and all-gather pairs; it is not usually another multiplier in the device mesh (Korthikanti et al. 2022). Selective activation recomputation complements SP by recomputing operations that are cheap relative to the memory they save.

Context parallelism (CP) divides the sequence through attention itself. Each rank owns local queries and passes or gathers key/value blocks needed to compute exact attention. Ring Attention streams those blocks around a ring while using an online softmax (Liu et al. 2023); all-to-all designs are another option. CP reduces local sequence storage, but dense attention still performs O(L2)O(L^2) global arithmetic for context length LL. Maximum context remains bounded by aggregate memory, communication, device count, and the degree to which communication can overlap computation.

Expert parallelism: split conditional parameters

Mixture-of-experts models add expert parallelism (EP). Tokens are routed to the ranks that hold their selected experts and the outputs are returned to the original token owners, commonly with all-to-all communication (Lepikhin et al. 2020). A forward pass often has a dispatch and a combine exchange; backward sends the corresponding gradient traffic. Hot experts cause stragglers, so routing locality, load balance, optional capacity padding, and dropless kernels are systems concerns as well as modeling choices. The routing objective itself is covered in Chapter 9.

Figure 10.4 summarizes what each axis moves. The collective names are common implementations, not promises: frameworks can fuse, decompose, or schedule them differently.

axes t Axis Divides Common communication DDP batch; model state replicated gradient all-reduce ZeRO-3 / full-shard FSDP batch and all persistent model state parameter all-gather, gradient reduce-scatter TP matrix multiplications within a layer all-reduce or reduce-scatter/all-gather PP consecutive layer groups point-to-point activations and gradients SP TP-replicated activation regions reduce-scatter and all-gather on TP group CP sequence through attention key/value ring exchange or all-to-all EP expert parameters and routed tokens dispatch and combine all-to-all
Figure 10.4. Parallelism axes by the state they divide and the communication they commonly introduce. SP usually reuses the TP group; the other degrees may form independent mesh dimensions.

Map the cuts onto the network

For independent data, tensor, pipeline, and context dimensions, a dense-model mesh satisfies

N=DTpC.N = D T p C.

Here, NN is the world size, DD the data-parallel degree, TT the tensor-parallel degree, pp the number of pipeline stages, and CC the context-parallel degree. SP normally shares the TT group. EP is model-dependent: its group may be carved from or overlap another mesh dimension, so blindly multiplying by an expert degree can double-count devices.

The placement principle is simple: put the most frequent and latency-sensitive exchanges inside the fastest fabric domain. TP often gets that domain because it communicates inside every layer. EP needs strong bisection bandwidth for all-to-all traffic. PP message size depends on the boundary activation, while ZeRO-3/FSDP repeatedly gathers parameters. Which axis crosses a node or rack boundary is therefore a measurement-driven choice, not a fixed hierarchy (Narayanan et al. 2021).

mesh workers N accelerators groups logical groups DP × TP × PP × CP workers->groups assign ranks topology physical fabric links, switches, failure domains groups->topology place groups profile measured step compute, exposed communication, stalls topology->profile run and trace profile->groups revise layout
Figure 10.5. A device mesh is a set of communication groups over the same workers. Frequent TP exchanges are usually placed on the fastest links; DP, PP, CP, and EP placement depends on payload, topology, and available overlap.

Collectives have different semantics. An all-reduce reduces values and gives every rank the result. A reduce-scatter reduces and leaves each rank one shard. An all-gather concatenates shards on every rank. An all-to-all sends a distinct shard to each peer. PP mostly uses point-to-point send and receive. Libraries such as NCCL implement several algorithms for these operations and select among them according to the hardware and message shape (NVIDIA 2024).

Communication is necessary work, but only its exposed part extends the step's critical path. FSDP can gather the next unit while the current unit computes; gradient buckets can reduce during backward; PP and EP messages can overlap nearby kernels. Overlap is not free: communication may contend with compute for memory bandwidth, execution resources, or the network. A step trace, rather than a list of enabled flags, shows whether the overlap worked.

Lower-layer constraint

The physical network limits the logical mesh. Link bandwidth and latency, switch oversubscription, routing, and failure domains determine which groups can communicate frequently without stalling. The accelerator and fabric model described in Chapter 62 must therefore be part of every parallel-layout benchmark. A mesh tuned on one cluster is not automatically portable to another.

Choose numerical formats per operation

Mixed precision is not one global dtype. A common recipe performs large matrix multiplications in a low-precision format, accumulates reductions more carefully, and keeps sensitive operations or optimizer state in a wider format. The original mixed-FP16 recipe used FP32 master parameters, FP32 accumulation, and loss scaling (Micikevicius et al. 2017). BF16 has eight exponent bits and therefore roughly FP32's normal range, so it usually avoids FP16's loss scaling; its seven fraction bits still make accumulation and small updates precision problems.

FP8 offers two common layouts: E4M3 spends more bits on precision, while E5M2 spends more on range (Micikevicius et al. 2022). Values must be scaled into the representable interval, and the scaling granularity, whether tensor, tile, or block, is part of the recipe. Hopper-class hardware can have twice BF16's peak dense matmul rate for FP8 and FP8 operands use half as many payload bytes, but casts, scale metadata, non-matmul work, and retained high-precision state reduce the end-to-end gain.

DeepSeek-V3 demonstrated a full pre-training run whose core matrix multiplications used FP8, while several sensitive operations and outputs stayed in BF16 or FP32 (DeepSeek-AI 2024). A later NVIDIA experiment trained a 12B model for ten trillion tokens with NVFP4 and reported results comparable to an FP8 baseline, using fine-grained scaling, Hadamard transforms, stochastic rounding, and selective higher precision (NVIDIA 2025). These are measured recipes, not evidence that every model or operation can be lowered safely.

Figure 10.6. Where each floating-point format spends its bits. Exponent width controls range; mantissa width controls precision. Block-scaled FP4 formats attach additional scale metadata that this value-level layout does not show.
precision t format sign exponent mantissa FP32 1 8 23 FP16 1 5 10 BF16 1 8 7 FP8 E4M3 1 4 3 FP8 E5M2 1 5 2 FP4 E2M1 1 2 1
Figure 10.7. Value-level bit layouts used in training. A complete numerical recipe also specifies accumulation dtypes, scaling granularity and history, and which operations remain in higher precision.

A robust update has an explicit order: accumulate all micro-batches; unscale FP16 gradients if loss scaling is active; check finite values across all ranks; compute any global gradient norm over the logical, fully sharded gradient; clip if configured; then update every shard or skip the update everywhere. Scaling state, including FP8 amax history or a dynamic loss scaler, belongs in the checkpoint. Narrow formats can cause underflow, saturation, Inf/NaN values, skipped steps, divergence, or quiet quality drift. Validation must look for all of them.

What's contested

The lowest reliable training format remains recipe-dependent. Published FP8 and FP4 runs establish that particular models, scaling rules, accumulation paths, and hardware can work; they do not establish a universal precision floor. The useful question is therefore not "Does FP4 work?" but "Which tensors and operations can use this format for this run, under which validation thresholds?"

Measure throughput without hiding assumptions

Model FLOPs utilization (MFU) compares observed model work with a stated hardware peak (Chowdhery et al. 2023):

MFU=rtokFmodel,tokNPpeak.\mathrm{MFU}= \frac{r_{\mathrm{tok}}F_{\mathrm{model,tok}}} {N P_{\mathrm{peak}}}.

Here, rtokr_{\mathrm{tok}} is aggregate observed tokens per second, Fmodel,tokF_{\mathrm{model,tok}} is the forward-plus-backward FLOP count required by the model per token, NN is the accelerator count, and PpeakP_{\mathrm{peak}} is the matching-precision peak FLOP rate of one accelerator. The report must state the FLOP convention, how active MoE parameters and padding are treated, the precision peak used, and the measurement window.

Hardware FLOPs utilization (HFU) instead counts executed FLOPs, including activation recomputation. HFU can therefore exceed MFU even when useful-token throughput is unchanged. Neither metric proves training quality or reliability. Steady-state MFU commonly excludes restart time; end-to-end goodput should also charge failed steps, checkpoints, evaluation pauses, and input stalls.

When MFU is low, inspect a trace before changing the mesh. The usual causes are small or poorly shaped kernels, stage imbalance, exposed communication, excessive recomputation, input stalls, and synchronization behind a straggler. Peak memory, collective duration by group, tokens per second, step-time tails, and time lost to recovery complete the operational picture.

Make restart a correctness property

In an ordinary synchronous job, one failed rank invalidates its communicators. Elastic launchers generally stop and rebuild the worker group, then load a committed checkpoint; they do not hot-swap one device into a running collective. The control sequence is: detect the lack of progress, abort communication, fence or quarantine the suspect worker, replace capacity, rendezvous, rebuild groups, load a validated checkpoint, verify the data cursor, and resume.

A recoverable checkpoint is an atomic set, not merely a parameter file. It contains model and any master parameters; optimizer tensors and step; learning-rate state; loss-scaler and low-precision scale history; per-rank RNG state; sampler, shuffle, data-mixture counters, and cursor; plus a shard manifest, checksums, and a completion marker. Saving at an optimizer-step boundary avoids storing partially accumulated gradients. Keep more than the latest checkpoint because a numerically damaged state may already have been saved.

There are two legitimate resume contracts. Deterministic replay attempts the same batches and random draws and usually requires the same topology plus deterministic kernels. Coverage-equivalent resume may reshard onto a different world size while preserving which data is consumed overall. It need not be bitwise identical. State the contract and test it.

Checkpoint cadence trades write cost against repeated work. A first-order fail-stop model gives

W(τ)Cτ+τ2M,τ2CM.W(\tau)\approx\frac{C}{\tau}+\frac{\tau}{2M}, \qquad \tau^\star\approx\sqrt{2CM}.

Here, W(τ)W(\tau) is the expected fraction of time lost to checkpointing and recomputation, τ\tau is useful compute time between checkpoints, CC is the exposed checkpoint cost, MM is the synchronized job's mean time between interruptions, and τ\tau^\star is the approximate minimizing interval (Daly 2006). The approximation assumes independent fail-stop events and omits correlated outages, recovery delay, and storage contention. Asynchronous checkpointing lowers exposed CC, but still consumes device links, host memory, network capacity, and storage bandwidth. CheckFreq demonstrates adaptive cadence and pipelined snapshot/persist phases rather than a free write (Mohan et al. 2021).

Verify the layout before a long run

A distributed configuration is ready only after it passes small, deliberate tests:

  • Update equivalence: on a tiny deterministic batch, compare the unsharded and sharded loss, gradients, and one optimizer update within a stated tolerance.
  • Memory accounting: measure persistent, peak, and temporary memory while sweeping micro-batch and sequence length. Confirm that the wrapped-unit and prefetch assumptions match the trace.
  • Communication accounting: profile each group and identify exposed rather than merely total communication. Test the planned cross-node boundaries.
  • Numerical stability: compare a higher-precision control with the proposed per-operation recipe; record nonfinite tensors, skipped steps, pre-clip gradient norms, clipped-step frequency, and evaluation drift.
  • Restart correctness: kill a worker during compute and during checkpoint persistence. Reject incomplete manifests, restore the declared data contract, and compare the resumed trajectory with the control.
  • Goodput: run long enough to include checkpoints, input loading, and at least one recovery. Report useful tokens per wall-clock second alongside MFU.

FlashAttention illustrates why every layer of this accounting matters. It computes exact attention without materializing the full score matrix in HBM (Dao et al. 2022). For batch size BB, head count HH, context length LL, and bb bytes per score element, materializing the scores alone would use

Mscore=BHL2b.M_{\mathrm{score}} = BHL^2b.

Here, MscoreM_{\mathrm{score}} excludes softmax workspace, inputs, outputs, saved activations, and allocator overhead. FlashAttention removes this quadratic HBM tensor, but it does not remove the dense attention arithmetic or the need to shard a context that exceeds aggregate memory.

2026-08-03T21:55:27.889175 image/svg+xml Matplotlib v3.11.0, https://matplotlib.org/ 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 context length L (thousands of tokens) 2 8 2 5 2 2 2 1 2 4 2 7 2 1 0 tensor size (GiB) materialized scores (B×H×L²) one token-state tensor (B×L×d)
Figure 10.8. Exact byte accounting for a materialized attention-score tensor versus one token-state tensor, using B=1, H=32, hidden width 4096, and BF16 storage. The linear token-state line is a reference, not a model of FlashAttention's complete peak memory.

The same discipline applies to the whole run: name the tensor, count its bytes, identify when it exists, and state which communication or recovery step follows. That turns a collection of parallelism acronyms into an engineering design that can be checked.

Further reading

  • Shoeybi et al., “Megatron-LM: Training Multi-Billion Parameter Language Models Using Model Parallelism,” 2019. arXiv:1909.08053
    Megatron-LM presents an intra-layer tensor-parallel formulation for Transformer training and measures its communication and scaling behavior.
  • Rajbhandari et al., “ZeRO: Memory Optimizations Toward Training Trillion Parameter Models,” 2020. arXiv:1910.02054
    ZeRO partitions optimizer state, gradients, and parameters to remove memory redundancy from data-parallel training while changing communication schedules.
  • Narayanan et al., “Efficient Large-Scale Language Model Training on GPU Clusters Using Megatron-LM” (SC'21; PTD-P 3D parallelism), 2021. arXiv:2104.04473
    The paper composes tensor, pipeline, and data parallelism and analyzes pipeline schedules for large Transformer training.
  • Korthikanti et al., “Reducing Activation Recomputation in Large Transformer Models” (sequence parallelism + selective recomputation), 2022. arXiv:2205.05198
    This paper introduces sequence parallelism and selective activation recomputation to reduce activation memory by 5x and cut activation recomputation overhead by over 90% when training large transformer models with tensor parallelism.
  • Huang et al., “GPipe: Efficient Training of Giant Neural Networks using Pipeline Parallelism” (NeurIPS), 2019. arXiv:1811.06965
    GPipe proposes pipeline parallelism via micro-batch splitting to scale neural networks beyond single-accelerator memory limits with near-linear speedup across multiple accelerators.
  • Narayanan et al., “PipeDream: Generalized Pipeline Parallelism for DNN Training” (SOSP), 2019. doi.org
    PipeDream combines pipeline parallelism with data parallelism to reduce inter-GPU communication by up to 95% and achieve up to 5x faster time-to-accuracy than data-parallel DNN training.
  • Zhao et al., “PyTorch FSDP: Experiences on Scaling Fully Sharded Data Parallel” (VLDB), 2023. arXiv:2304.11277
    The FSDP paper explains how parameter sharding interacts with PyTorch autograd, allocation, communication, and state management.
  • Rajbhandari et al., “ZeRO-Infinity: Breaking the GPU Memory Wall for Extreme Scale Deep Learning,” 2021. arXiv:2104.07857
    ZeRO-Infinity is a heterogeneous training system that offloads model states to CPU and NVMe memory, enabling training of models with tens of trillions of parameters on existing GPU clusters without model code refactoring.
  • Micikevicius et al., “Mixed Precision Training,” 2017. arXiv:1710.03740
    This paper presents mixed precision training, combining FP16 storage and arithmetic with FP32 master weights, loss-scaling, and FP32 accumulation to halve memory use without accuracy loss.
  • Micikevicius et al., “FP8 Formats for Deep Learning,” 2022. arXiv:2209.05433
    The paper specifies E4M3 and E5M2 FP8 interchange formats and evaluates training recipes across several neural-network families.
  • DeepSeek-AI, “DeepSeek-V3 Technical Report” (fp8 pre-training at frontier scale), 2024. arXiv:2412.19437
    Reports DeepSeek-V3, a 671B-parameter Mixture-of-Experts model with 37B active per token, trained on 14.8T tokens with fp8 matmuls and auxiliary-loss-free load balancing, rivaling closed models at low cost.
  • NVIDIA, “Pretraining Large Language Models with NVFP4” (4-bit pre-training with microscaling), 2025. arXiv:2509.25149
    Trains a 12B model over 10 trillion tokens in the NVFP4 4-bit microscaling format, using Random Hadamard transforms, two-dimensional scaling, and stochastic rounding to match an fp8 baseline.
  • Hu et al., “Elucidating the Design Space of FP4 training” (what makes 4-bit training hold), 2025. arXiv:2509.17791
    Maps the design space of 4-bit training across block-scaled formats, Hadamard transforms, and stochastic rounding, identifying which combinations keep fp4 matmuls near baseline quality at acceptable overhead.
  • Dao et al., “FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness” (kernel-level IO-awareness; also in 03), 2022. arXiv:2205.14135
    Dense FlashAttention computes exact attention with IO-aware tiling, reducing HBM traffic and avoiding materialization of the full score and probability matrices.
  • Liu et al., “Ring Attention with Blockwise Transformers for Near-Infinite Context” (context-parallel attention), 2023. arXiv:2310.01889
    Ring Attention distributes long sequences across multiple devices in a ring topology, overlapping key-value block communication with blockwise self-attention computation to enable near-infinite context length without approximations.
  • Lepikhin et al., “GShard: Scaling Giant Models with Conditional Computation and Automatic Sharding” (expert sharding + all-to-all; also in 04), 2020. arXiv:2006.16668
    GShard introduces lightweight annotation APIs and an XLA compiler extension enabling automatic SPMD sharding of a 600B-parameter MoE Transformer trained on 2048 TPU v3 devices for multilingual translation across 100 languages.
  • NVIDIA, “NCCL: NVIDIA Collective Communications Library” (optimized inter-GPU collective primitives (all-reduce, all-gather, reduce-scatter, all-to-all) over NVLink/PCIe/InfiniBand; engineering library, not a single canonical paper), 2024. github.com
    NCCL implements topology-aware collective communication primitives for moving tensors among NVIDIA GPUs within and across nodes.
  • Mohan et al., “CheckFreq: Frequent, Fine-Grained DNN Checkpointing” (USENIX FAST'21; asynchronous, low-overhead checkpointing), 2021. usenix.org
    CheckFreq profiles checkpoint cost, adjusts save frequency, and pipelines checkpoint work while preserving its evaluated data-loader invariant.
  • Xu et al., “GSPMD: General and Scalable Parallelization for ML Computation Graphs” (XLA/TPU sharding annotations underlying JAX `pjit`), 2021. arXiv:2105.04663
    GSPMD propagates tensor-sharding annotations through a computation graph and emits a partitioned single-program, multiple-data program.

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