Making the Silicon: Packaging, HBM, and the Geopolitics of Compute

Chapter 66 treated the memory wall and the reticle limit as design constraints: facts the architect of an accelerator must build around. Now the same silicon becomes a supply chain, and the question gets blunter. Granting that the design is sound, can a frontier accelerator be built, and how many? In 2026 the binding constraint on AI compute moved down the stack from the transistor to the package and the memory stack. A few square centimeters of silicon interposer can rate-limit the whole field; a memory shortage now reaches all the way out to laptops and phones; export controls and sovereign-compute programs become the levers by which states ration a scarce industrial good.

The bottleneck moved below the transistor

For two decades the frontier of semiconductors was lithography: the binding question was whether the next node, each one a new generation of chip manufacturing, could print smaller transistors. That is no longer where AI compute is gated. Leading-edge logic is ramping on schedule, TSMC's N2 node is in production, and the next lithography leap, High-NA extreme ultraviolet, has been deliberately deferred to roughly the end of the decade because multi-patterned standard EUV remains cheaper per good die. The transistor is not the bottleneck. The bottleneck moved to two places the Chapter 66 chapter named as design facts and this chapter treats as scarce goods: the silicon interposer that tiles chiplets and memory into one package, and the stacked DRAM that supplies the bandwidth.

The reason is the one Chapter 66 established and this chapter will not re-derive: a frontier accelerator exceeds the single-reticle limit, so it must be assembled on an interposer rather than printed as one die. That makes advanced packaging, specifically TSMC's CoWoS-L line, the per-unit gate on how many frontier accelerators can exist. Through 2026 that line ran fully booked, with lead times reported at a year and more, even as TSMC scaled it from roughly 35,000 wafers per month toward 120,000 and beyond and projected an eleven-fold rise in AI wafer demand across 2022 to 2026 (TrendForce 2026). A single buyer, NVIDIA, holds the majority of total CoWoS capacity and a larger share of CoWoS-L specifically, which is why a competitor's launch schedule can be set as much by interposer allocation as by its own design.

Two gates that take turns

The defining feature of the 2026 supply chain is that the binding constraint oscillates between two chokepoints, quarter by quarter, so naming a single bottleneck is already a simplification. The first is the interposer. The second is the memory.

HBM4, the memory generation that frontier accelerators use, is not merely a faster DRAM. It doubles the interface to a 2,048-bit bus, runs at roughly 11 gigabits per second per pin at the frontier rather than the 8 the standard baseline specifies, and, most consequentially, places a logic die fabricated on a foundry process at the base of each stack (SK hynix 2025). That last change couples memory to logic: HBM volume now competes for leading-edge foundry capacity rather than being purely a DRAM-fab problem, so the two gates are not independent. By mid-2026 all three memory makers, SK hynix, Samsung, and Micron, had been qualified for the frontier accelerator's HBM4 and were in production, and all three had declared their output sold out before the year began. The power-efficiency gains the vendors quote differ enough to matter: SK hynix claims better than forty percent over its prior generation, Micron a more modest figure, so the generation is not a single uniform step.

The interposer roadmap is the supply-side clock. TSMC's public path runs from roughly 5.5 reticles of CoWoS-L area carrying a handful of HBM stacks today, through a fourteen-reticle generation with twenty stacks around 2028, to a beyond-fourteen-reticle package with twenty-four HBM stacks near 2029, at a reported packaging yield already around ninety-eight percent (TrendForce 2026). That yield figure carries a lesson: at the CoWoS-L tier the problem is no longer whether a package can be made well, but how many can be made at all. Capacity, not yield, is the gate. One layer deeper, in the true three-dimensional stacking of SoIC, where dies are bonded copper-to-copper rather than laid side by side, yield and capacity are both still hard, which is why SoIC is the chokepoint most likely to bind after CoWoS-L eases.

The shortage reaches the laptop

The story the design-side chapter could not tell is what the memory gate does to everything that is not a frontier accelerator. Because an HBM stack consumes several times the wafer area per gigabyte of a commodity DRAM chip, and because the memory makers have shifted their best capacity to HBM, the AI build-out is now cannibalizing the supply of ordinary memory. Through late 2025 and into 2026 this surfaced as a broad memory supercycle: contract prices for standard server DRAM more than doubled, makers pruned or exited consumer lines, and the cost of memory in a phone or a laptop rose because the fab that would have made it is making HBM for accelerators instead. The constraint arrow that began at the top of the accelerator now runs all the way down into consumer electronics: AI compute competes with all of computing for a shared pool of fab output, and through 2026 AI was winning.

Geography is policy

Almost all of this capability sits in one place. Leading-edge logic, the CoWoS-L interposer line, and the packaging yield learning are concentrated in Taiwan, with memory concentrated in South Korea. That concentration turns a supply chain into a geopolitical instrument, and the instrument was used heavily across the period this book covers.

The United States has rationed access to frontier compute through export controls that tightened in steps: the original 2022 cutoff on the fastest parts, then performance-throttled variants engineered to sit just under each new threshold, and in January 2026 a shift to case-by-case review for H200-class and competitor parts bound for China, defined by concrete limits on total processing performance and on memory bandwidth, and paired with a revenue tariff and a volume cap (U.S. Bureau of Industry and Security 2026). The thresholds are not incidental: a bandwidth ceiling as an export-control knob is the policy world conceding the same point as Chapter 66, that the scarce quantity is bytes per second, not raw arithmetic.

What the controls have actually done is the chapter's live debate. They have not let a Chinese accelerator match the Western frontier on a per-chip basis, and the binding shortage on the Chinese side is HBM rather than logic, since domestic foundries can approximate a usable logic node but cannot yet supply frontier-generation memory, though domestic HBM a generation or two behind began shipping in 2026 (TrendForce 2025). They have also unmistakably accelerated indigenization, which is why the Huawei CloudMatrix scale-up domain of Chapter 66 exists at all: when the best chips are forbidden, the answer is more chips and more watts. Whether the controls slow the Chinese frontier or harden it is the question the policy community is split on, and it is genuinely open.

Supply as an architectural gate

At this layer, capability, efficiency, and trust stop looking like model properties, and that is the point. Capability here is not a property of a model or even a chip; it is a question of allocation, of whether interposer area and memory stacks can be secured at all, so the frontier is partly a procurement frontier. What counts as efficiency here is physical: the wafer-area cost of a gigabyte and the yield of a package, the quiet variables that decide how many accelerators a fixed fab output becomes. Trust reduces to supply security and concentration, and a field whose entire frontier depends on a few lines in two countries, rationed by export policy, is trusting a supply chain as much as it trusts any algorithm. The accelerator of Chapter 66 is the artifact; this chapter is the gate it must pass through. The next chapter follows the finished accelerator to the wall socket, where a third scarce good, electricity, binds on a timescale even longer than a sold-out packaging line.

Further reading