Making the Silicon: Packaging, HBM, and the Geopolitics of Compute

Chapter 66 ended at the boundary of the accelerator package. This chapter follows the design into manufacturing and asks a different question: how many qualified systems can actually ship in a stated product and time window?

It is common to say that the bottleneck has moved down the stack from the transistor to the package and the memory stack. That can be true for a particular product, quarter, and allocation, but it is not universal. A silicon interposer can rate-limit one build while known-good logic dies, package substrates, HBM stacks, assembly tools, final test, or a legal restriction can bind another. A memory shortage now reaches all the way out to laptops and phones only when shared equipment, product mix, inventories, and contracts transmit the pressure. In turn, export controls and sovereign-compute programs alter access, but neither creates physical capacity by decree.

The useful object is therefore not a story about one permanent bottleneck. It is a dated supply ledger for one bill of materials, ending at a qualified shipment.

A package is a bill of materials, not one bottleneck

A modern accelerator package can combine several logic dies, several HBM stacks, an interposer or redistribution structure, and a package substrate. Those components pass through different manufacturing and test flows before they meet. The shippable quantity is bounded by the scarcest compatible input or downstream operation, all measured over the same interval.

For a product with a fixed bill of materials, an optimistic upper bound is

$$N_{\text{ship}} \le \min\!\left( \left\lfloor\frac{G_L}{d}\right\rfloor, \left\lfloor\frac{G_H}{h}\right\rfloor, \left\lfloor\frac{G_I}{i}\right\rfloor, \left\lfloor\frac{G_S}{s}\right\rfloor, C_A, C_T \right).$$

where:

• $N_{\text{ship}}$ is the number of accelerators that pass final acceptance in the stated time window;
• $G_L$ is the inventory of qualified known-good logic dies, and $d$ is the number of logic dies required per accelerator;
• $G_H$ is the inventory of qualified good HBM stacks, and $h$ is the number of HBM stacks required per accelerator;
• $G_I$ is the inventory of good interposers, and $i$ is the number required per accelerator;
• $G_S$ is the inventory of qualified package substrates, and $s$ is the number required per accelerator;
• $C_A$ is assembly and bonding capacity, measured in packages over the same interval; and
• $C_T$ is final-test and qualification capacity, also measured in packages over that interval.

Logic supply can itself be decomposed as

$$G_L = W_L D_L Y_L,$$

where:

• $W_L$ is the number of logic wafers completed for this product in the interval;
• $D_L$ is the candidate dies per completed wafer after edge and test-structure losses; and
• $Y_L$ is the fraction accepted as known-good dies at the specified wafer probe and binning boundary.

The bound is deliberately optimistic. Matching compatible bins, safety stock, scrap, rework, transport, allocation priority, and legal holds can all reduce actual shipments. It is still useful because it forces every number into a unit that can become one finished package.

The following illustrative ledger uses no vendor forecast. It only shows the unit conversion. Change an inventory or bill-of-materials count to see the binding stage move.

package_equivalents = {
    "known-good logic dies": 7_200 // 2,
    "qualified HBM stacks": 12_500 // 4,
    "good interposers": 4_100 // 1,
    "qualified substrates": 3_800 // 1,
    "assembly capacity": 3_500,
    "final-test capacity": 3_400,
}

binding_stage = min(package_equivalents, key=package_equivalents.get)
print(f"Binding stage: {binding_stage}")
print(f"Optimistic shipment bound: {package_equivalents[binding_stage]:,}")

From wafer start to known-good die

Wafer starts are not shipments. A wafer start enters a fabrication flow; a processed wafer has completed that flow; candidate dies are the patterned die locations that could become products; and known-good dies are the dies that meet a stated wafer-probe and binning contract. Confusing these units is the fastest way to turn a plausible capacity number into an implausible shipment forecast.

The physical sequence also matters. After fabrication, wafer probe screens individual dies before singulation and expensive package assembly. In a multi-die package, early screening limits the value destroyed when one bad component invalidates an otherwise good assembly. Yet “known good” is not an absolute property. It depends on test coverage, operating corners, binning, and the failures that can only be observed after assembly or burn-in. The IEEE Electronics Packaging Society therefore treats heterogeneous-integration test as a sequence of compromises, not a single perfect screen (IEEE Electronics Packaging Society Test Technical Committee 2022).

Yield must retain the same boundary discipline. Die yield, HBM stack yield, interposer or package-substrate yield, assembly yield, and final-test yield are different quantities. A high yield reported at one step neither proves high end-to-end yield nor proves that capacity, rather than yield, binds the product.

A reticle field limits the area patterned by a conventional single-exposure die. It does not imply that every accelerator must exceed that field or use a silicon interposer. Designers can choose a monolithic die, multiple chiplets, 2.5D or 3D integration, or a stitched or wafer-scale design. Each route moves cost and risk between die yield, interconnect, package assembly, cooling, and test. TSMC's CoWoS platform is one commercially important 2.5D route: its public description places logic and HBM on an interposer and supports interposers larger than two reticle fields (TSMC 2026). Its 2026 roadmap described 5.5-reticle CoWoS in production and a 14-reticle version planned for 2028 (Taiwan Semiconductor Manufacturing Company 2026). “In production” and “planned” are different evidence states.

HBM and advanced packaging are coupled, not interchangeable

An HBM stack is not one homogeneous die. It contains DRAM dies connected vertically and a base die that provides interface and control functions. HBM4 doubles the interface width to 2,048 I/O connections. In September 2025, SK hynix said it had completed HBM4 development and prepared a mass-production system, while reporting a product speed above 10 Gb/s per pin (SK hynix 2025). Micron's product page describes a 2,048-I/O HBM4 device with more than 2.8 TB/s of stack bandwidth (Micron Technology 2026). These are vendor and product claims, not evidence that every accelerator has qualified either part or that allocated volume is available to every buyer.

The logic base die adds a foundry dependency, but it does not mean the whole HBM stack consumes the same leading-edge wafer process as a compute die. The DRAM dies remain memory-fab products. TSMC has publicly offered both N12 and N3 logic base-die options for HBM4 (Taiwan Semiconductor Manufacturing Company 2025). Which process is used is product-specific, as are stacking, thermal, package, and qualification requirements.

Packaging and HBM are therefore coupled through one product schedule, not interchangeable as capacity units. A good interposer cannot replace a missing HBM stack. Unqualified HBM cannot fill a qualified allocation. Production capability, customer qualification, contractual allocation, and accepted shipment are four separate milestones.

Capacity claims need an evidence contract

Public supply claims often mix incompatible statuses. A disciplined ledger labels each claim before using it:

The record also needs an as of date, a product and site scope, and a unit boundary. “Wafers per month” might mean wafer starts, processed wafers, interposer wafers, or an analyst's normalized estimate. None can be converted directly into assembled packages without die area, yield boundaries, package configuration, downtime, and allocation. Installed capacity is not available capacity, and available capacity is not committed allocation.

Roadmaps deserve the same care. TSMC's April 2026 announcement separates a 5.5-reticle package it said it was producing from a 14-reticle package slated for 2028 (Taiwan Semiconductor Manufacturing Company 2026). A roadmap is useful for architecture planning, but it should not enter a current-quarter supply ledger as inventory.

Spillovers are opportunity-cost mechanisms

HBM demand can affect conventional DRAM, but “more HBM means fewer laptop chips” is not an identity. The effect requires a transmission mechanism: shared clean-room space or equipment, engineering attention, capital budgets, supplier inputs, and a product-mix decision. Inventories, long-term contracts, and dedicated lines can delay or absorb the pressure. New capacity can weaken it.

The practical test is counterfactual: if the HBM order disappeared, which specific tool time, wafer flow, material, or capital project would move to the other product, on what schedule? Without that bridge, a concurrent HBM ramp and consumer-memory price change is correlation, not a complete causal account. Chapter 76 develops the corresponding opportunity-cost logic at the industry level.

Geography is a stage map

Country labels hide the supply chain they are meant to explain. One package can depend on design and EDA, lithography tools, wafers and chemicals, logic fabrication, DRAM fabrication, interposer processing, substrates, assembly, test, and customer qualification in different places. The Semiconductor Industry Association describes the chain as globally integrated across design, fabrication, and assembly, test, and packaging (Semiconductor Industry Association and Boston Consulting Group 2021). TSMC's own 2025 capacity page lists fabrication in Taiwan and facilities or subsidiaries in the United States, Japan, and China (Taiwan Semiconductor Manufacturing Company 2026). That does not make all sites interchangeable: process, product, volume, and qualification differ.

An alternate site reduces risk only after its output is qualified and its materials, tools, utilities, logistics, test flow, and customer acceptance are available at the required volume. Announced construction is therefore an option on future resilience, not present substitution. Public programs can help create options: for example, the U.S. Department of Commerce announced advanced-packaging research and pilot-line awards in January 2025 (U.S. Department of Commerce 2025). Their status and scale still have to be compared with the production need they are supposed to cover.

Export controls are executable predicates

An export-control statement is incomplete without its date and transaction scope. At minimum, record the item parameters, destination, end use, end user and ownership, applicable list or rule, license policy, license conditions, and the jurisdictional basis for the export, reexport, or in-country transfer. The result is a legal predicate attached to a transaction, not a color on a map.

The January 15, 2026 BIS final rule illustrates the point. For certain exports from the United States to end users in China or Macau, it set a case-by-case review path for commodities below a total processing performance of 21,000 and total DRAM bandwidth of 6,500 GB/s, subject to certifications and other conditions (U.S. Bureau of Industry and Security 2026). This description was verified against the final rule on August 7, 2026. The same rule retained a presumption of denial for specified reexports, transfers, destinations, ownership cases, and overlapping policies. Case-by-case review is not approval. It means the application is evaluated under that policy after the threshold, scope, and conditions are met. For an actual transaction, the current Export Administration Regulations and current party-screening results control, not this summary.

Memory bandwidth appears in that rule as one classification parameter. That does not prove a general economic claim that bandwidth is always scarcer than arithmetic. Legal thresholds define a control boundary; measurements and the supply ledger identify the physical constraint.

How to verify supply

A procurement claim becomes reproducible when another reviewer can reconstruct its numerator, denominator, scope, and evidence. For each critical component or operation, capture:

1. product, BOM revision, approved supplier and site, and qualification version;
2. capacity unit, unit boundary, allocation period, and as-of date;
3. committed and forecast quantities in separate fields;
4. yield boundary, test coverage, sampling rule, and acceptance owner;
5. lead-time percentile rather than only an average;
6. inventory location, safety-stock policy, and allocation priority;
7. alternate qualification status and time to switch; and
8. failure trigger, recovery plan, and evidence owner.

Then run scenarios against the same ledger: loss of one site, lower HBM yield, delayed substrate delivery, final-test saturation, or a legal hold. A useful review does not merely say “diversified.” It reports which accepted shipments survive, for how long, and which evidence will show that recovery has begun.

What's contested

• Which stage is binding? The answer can change by product, customer, site, week, and qualification state. Public booking claims are weak evidence without a common unit boundary; accepted shipments and queue data are stronger, but rarely public.
• How strongly does HBM displace ordinary DRAM? Shared tools and capital create opportunity cost, while dedicated processes, inventory, contracts, and new investment interrupt it. The size and lag of the spillover are empirical questions.
• Does geographic duplication create resilience? A second facility adds option value, but only qualified volume plus working upstream and downstream dependencies creates substitution. Whether the benefit justifies its cost depends on the failure scenario and recovery target.
• What do export controls change? Rules can reduce access to specified products and transactions. Their longer-run effects on substitution, domestic investment, performance, and security require counterfactual evidence; the rule text alone cannot settle them.

The durable skill is to reconcile evidence at one unit boundary. Start from a qualified shipment, work backward through its current BOM and test contract, and preserve the date, status, site, and legal scope of every claim. That turns “the chip supply chain” from a dramatic but vague bottleneck story into a model that procurement, engineering, finance, and policy teams can challenge together. The next chapter, Chapter 68, applies the same discipline to power: another resource whose name is simple and whose deliverable capacity is not.

Further reading